1. Field of the Invention
The invention relates to semiconductor integrated circuits and particularly to read only memories.
2. Description of the Prior Art
The read only memory (ROM) is a well-known circuit used in great quantities in computers, calculators and in almost all digital systems. Conventional integrated circuit ROMs include on a single chip not only the ROM array, which is made of ROM or memory cells, but also attendant circuits, such as input and output ports, address register and decoder, control, multiplexer, buffers, timing circuits and the interconnections. The size of the ROM, related to the number of cells in the array, is constantly growing and 32,000 bit ROM are presently commercially available. Current activity is to design still larger ones, 64K, and it is desirable to have still larger ones, all on a single chip.
A typical ROM cell has a single FET transistor with a source-drain connection that is either complete or open, e.g. inoperable. When the ROM cell is interrogated; and if it has an open circuit, then it gives an output signal of one logic level, e.g. a signal representing "1;" and if it has a completed circuit, it gives the other logic level, e.g. a signal representing "0."
In one type of ROM circuit, the FETs that make up the ROM array are fixed during fabrication. During one masking step selected ROM cells which are to give the logic "1" have their source drain circuit rendered effectively inoperable. Thus, each ROM cell has a permanently stored logic 1 or logic 0, and gives the logic 1 or logic 0 response to an input signal.
An introductory explanation of ROMs, the mask programmable ROM cell, the complete ROM array, and ROM chip, may be found in Brice Ward, MICRO PROCESSOR/MICRO PROGRAMMING HANDBOOK, 1975, Blue Ridge Summit, Pa.
A classic and historic goal in the design and manufacture of ROMs is to have more data on a single chip. Single chip ROMs in the past decade have increased from 256 bits to approximately 1,000 to 2,000, 4,000, 8,000, 16K, 32K, and talk is currently of 64K and larger. The present invention greatly increases, e.g. doubles, the capacity of a ROM chip, without substantially increasing its physical size, and makes possible 128K ROMs with current manufacturing capability using established metal gate processing. In other words, with the present invention, ROM arrays can be made using half the area previously required.
The concept can be quite simply stated. Instead of building a ROM array, as was done in the prior art, with the existence or non-existence of an operable FET in each cell, the ROM array of this invention uses a FET in each cell that has one of several different thresholds. If, for example, three thresholds are available (-2.0 volts, +0.1 volts, and +0.7 volts) then four states are now available for a given cell in the array (the fourth state, of course, is an inoperable, or non-existent FET). The four states can be compared with the prior art cell, which had only two states, and, in the prior art, to get four states two cells are required. In the present invention, the surface area of each cell is the same as each other cell, and the threshold level of each FET is not affected by this common size. Thus the invention doubles the memory size of the ROM array without increasing its physical size. Put in another way, the silicon area is halved.
Further, this invention makes possible ROMs of 128K bits by using existing metal gate processing techniques. It had been believed by some that to manufacture ROMs of 128K new process techniques would have to be perfected.
In the invention, the reduction in area is achieved by circuit innovation. The layout rules have not been compromised. Thus as new geometric shrink advances become available, the ROMs using the invention can take advantage of them.
In the present array, capacitance within the array is reduced; it is approximately halved. This has an effect on speed.
In the present invention, less power is required thus avoiding attendant problems of heating, and particularly heat dissipation. This is a classic goal in any memory array.
The manufacture of the invention is straight-forward. It does not require any radically different or new fabrication techniques from those currently in use, and which have been tried and tested. Further, as all the cells are of the same size, masking is straight-forward and thus easy to manufacture.